1. Field of the Invention
Embodiments of the present invention relate to a method of fabricating a semiconductor package, and a semiconductor package formed thereby.
2. Description of the Related Art
As the size of electronic devices continues to decrease, the associated semiconductor packages that operate them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die may be mounted. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), and shrink small outline packages (SSOP).
FIG. 1 shows a leadframe 20, and FIG. 2 shows the leadframe 20 after attachment of one or more memory die 22 and controller die 24. As seen in FIGS. 1 and 2, leadframe 20 includes leads 30 which are used to carry signals to and from the memory and controller die 22, 24. As seen in FIG. 2, the memory die 22 includes die bond pads 32, and the controller die 24 includes die bond pads 34. The leads 30 include internal ends 30a which may be connected to the die bond pads of the die 22 and 24 via wire bonds 38. The leads 30 may further include external ends (not shown), opposite internal ends 30a, which surface mount to pinout locations on a printed circuit board (PCB) or other host device to which the leadframe package is affixed.
In the package design, it is necessary to connect specific memory die bond pads 32 and specific controller die bond pads 34 to specific pinout locations via leads 30 of leadframe 20. Given conventional leadframes, an interposer 40 has been required to accomplish these connections. In particular, the configuration of the die bond pads 32 and 34 are set by the die manufacturers, without regard to the connections that will be required to electrically connect the die to the host PCB. Given the fact that electrical connections are not part of the die pad location design, when the electrical connections are made, some leads 30 are required to crossover other leads 30. As the leadframe 20 is only a single layer of metal, these crossovers would result in impermissible electrical shorts.
Thus, an interposer 40 is conventionally provided which has at least two layers. As seen in FIGS. 1 and 2, a first electrical connection, e.g., 42, is able to cross under a second electrical connection, e.g., 44, by a via 46 in the electrical connection 42 which routes the connection down to a second layer of the interposer 40, under connection 44, and then back up to the top layer of interposer 40 by a second via 48. This method may be used throughout the interposer to easily route connections from the die 22, 24 to the external leads and pinout locations.
One drawback to the use of an interposer is that its use on the leadframe adds time and expense to the fabrication process. It would be advantageous to provide a leadframe-based package where the semiconductor die are routed to the external leads of the leadframe without use of the interposer layer.